The present invention relates to a method for determining the optimum position of block pins that connect blocks, and processing optimally in this relation, when producing a large scale integrated circuit having a plurality of blocks buried in a chip. This invention also relates to a computer-readable recording medium into which a program for executing the method according to the present invention with a computer is recorded.
Hitherto, a large scale integrated circuit such as ASIC has been manufactured by preparing a plurality of blocks by using a hierarchical floor planner technique, and connecting block pins disposed in a region between the blocks.
The position determining process procedure of block pins by the conventional hierarchical floor planner will be explained with reference the flowchart shown in FIG. 13. First, the hierarchical floor planner prepares a plurality of blocks for composing a large scale integrated circuit, in a semiconductor chip (step S101). On the basis of the configuration of the blocks, block pin positions of each block are determined (step S102). Once the block pin positions are determined, cell disposition in each block is executed (step S103) When the cell disposition is completed, the block pins on the semiconductor chip are wired (step S104), and this process is finished. That is, the conventional hierarchical floor planner automatically performs the layout of blocks and wiring between blocks based on the determined block pin positions.
However, in such a conventional hierarchical floor planner, if the position of each block on the semiconductor chip is not appropriate, the wiring between blocks is redundant, and an unexpected timing error may occur depending on the wiring capacity.
Usually, for example, the layout in each block is not complete, and when determining each block pin position, the block pin position is determined only on the basis of the layout relation and connection relation between the blocks, but when the layout in each block is actually executed, since each block pin position is determined only on the basis of the layout relation and connection relation between the blocks, a cell for connecting each block pin is not always disposed near each block pin position. If the cell for connecting each block pin is not disposed near each block pin position, the wiring between the blocks is redundant.
It is an object of the present invention to provide a method for determining the optimum position of block pins capable of assuring each block pin position so that each block pin is disposed near a connection cell, and preventing occurrence of unexpected timing error, and a computer-readable recording medium recording a program for executing this method by a computer.
The method for determining the optimum position of block pins according to one aspect of this invention comprises a provisional position determining step of determining a block position to be disposed on a chip, and provisionally determining a block pin position of each block corresponding to the block position, a cell disposing step of executing a cell disposition in each block, and a pin position optimizing step of changing the position of the block pin to an optimum position corresponding to the cell connected to the block pin out of cells disposed at the cell disposing step. Thus, after determining the block position disposed on the chip, the block pin position of each block is provisionally determined at the provisional position determining step corresponding to the block position, and the cell disposition in each block is executed at the cell disposing step, then the block pin position is changed to the optimum position corresponding to the position of the cell connected to the block pin among the cells disposed at the cell disposing step, so that the distance between the block pin and the cell to which this block pin is connected may be always short.
The method for determining the optimum position of block pins according to another aspect of this invention comprises a provisional position determining step of determining a block position to be disposed on a chip, and provisionally determining a block pin position of each block corresponding to the block position, a dividing step of dividing into input and output blocks composed of cells relating to input and output logic circuits of the block pin and other internal block after provisional determination of the block pin at the provisional position determining step, an input and output block disposing step of executing a cell disposition in the input and output blocks, a pin position optimizing step of changing the block pin position to an optimum position corresponding to the cell position disposed at the input and output block disposing step, and an internal block cell disposing step of executing a cell disposition in the internal block. Thus, after determining the block position disposed on the chip, the block pin position of each block is provisionally determined at the provisional position determining step corresponding to the block position, after provisionally determining the block pin position at the provisional position determining step, the block is divided into the input and output blocks composed of cells relating to the input and output blocks of the block pin and other internal block at the dividing step, the cell disposition in the input and output blocks is executed at the input and output block disposing step, the block pin position corresponding to the cell position disposed at the input and output block disposing step is changed to the optimum position at the pin position optimizing step, and the cell disposition in the internal block is executed at the internal block cell disposing step.
Further, there are provided, an optimum adjusting step of optimally adjusting the delay timing of the input and output blocks after the block pin position is changed to the optimum position at the pin position optimizing step, and a correcting step of correcting a change portion by comparing between the cell disposition of the input and output blocks at the input and output block disposing step and the cell disposition of the input and output blocks optimally adjusted at the optimum adjusting step. Thus, after changing the block pin position to the optimum position at the pin position optimizing step, the delay timing of the input and output blocks is optimally adjusted by the optimum adjusting step, the change portion is corrected at the correcting step by comparing between the cell disposition of the input and output blocks disposed at the input and output block disposing step and the cell disposition of the input and output blocks optimally adjusted at the optimum adjusting step, and the distance between the block pin and the cell to which this block pin is connected is shortened, while the delay timing in the input and output blocks is optimally adjusted.
Further, the optimum adjusting step further adjusts the wiring delay between block pins of the block to be connected, and optimally adjusts the delay timing between other block to be connected and the internal block of the own block.
Further, the optimum adjusting step further adjusts the wiring delay between block pins of the block to be connected, and the delay of input and output blocks of other block to be connected, and optimally adjusts the delay timing between the internal block of other block to be connected and the internal block of the own block.
Further, the input and output blocks to be divided at the dividing step are input and output logic circuits between the block pin and a flip-flop circuit which forms input and output ends of the internal block.
A recording medium of the invention records a program to be executed by any one of the methods mentioned above by a computer.
According to the invention, by recording a program to be executed by any one of the methods mentioned above by a computer, the program is machine-readable, so that the operation of the method can be realized by the computer.